Input/output (IO) circuits in an integrated circuit (IC) can support a variety of IO standards, requiring a wide supply range. Advancements in IC fabrication technologies have resulted in IO transistors that have lower voltage limits across any two terminals thereof. Thus, it is becoming increasingly challenging to design IO circuits that can accommodate multiple IO standards across a wide supply range. One technique to address this challenge is to divide the wide supply range into high voltage and low voltage ranges. Two different data paths can be used to drive the IO pad in the high- and low-voltage modes. Similarly, two different receivers can be used to receive data from the IO pad in the high- and low-voltage modes. However, such implementations can result in glitches at the IO pad and at the output of the receivers when there is switching from one mode to the other mode (high-to-low or low-to-high). Such glitches are due to mismatch in delay for turn-off and turn-on of the two data paths. Such glitches can cause undesirable state changes, resets, and functional failures.